`timescale 1ns/1ns //仿真的单位/仿真的精度

module tb_uart_loopback();

//reg define
reg sys_clk_p; //差分时钟
reg sys_clk_n; //差分时钟
reg sys_rst_n; //复位信号
reg uart_rxd ; //UART 接收端口

//wire define
wire uart_txd ; //UART 发送端口

//*****************************************************
//** main code
//*****************************************************

//发送 8'h55 8'b0101_0101
initial begin
sys_clk_p <= 1'b0;
sys_clk_n <= 1'b1;
sys_rst_n <= 1'b0;
uart_rxd <= 1'b1;
#200
sys_rst_n <= 1'b1;
#1000
uart_rxd <= 1'b0; //起始位
#8680
uart_rxd <= 1'b1; //D0
#8680
uart_rxd <= 1'b0; //D1
#8680
uart_rxd <= 1'b1; //D2
#8680
uart_rxd <= 1'b0; //D3
#8680
uart_rxd <= 1'b1; //D4
#8680
uart_rxd <= 1'b0; //D5
#8680
uart_rxd <= 1'b1; //D6
#8680
uart_rxd <= 1'b0; //D7
#8680
uart_rxd <= 1'b1; //停止位
#8680
uart_rxd <= 1'b1; //空闲状态
end

//100Mhz 的时钟，周期则为 1/100Mhz=10ns,所以每 5ns，电平取反一次
always #5 sys_clk_p = ~ sys_clk_p;
always #5 sys_clk_n = ~ sys_clk_n;

//例化顶层模块
uart_loopback u_uart_loopback(
.sys_clk_p (sys_clk_p),
.sys_clk_n (sys_clk_n),
.sys_rst_n (sys_rst_n),
.uart_rxd (uart_rxd ),
.uart_txd (uart_txd )
);

endmodule